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| PRELIMINARY CG6257AM 4Mb (256K x 16) Pseudo Static RAM Features * Wide voltage range: 2.70V-3.30V * Access Time: 70ns * Ultra-low active power -- Typical active current: 2.0mA @ f = 1 MHz * * * * -- Typical active current: 13mA @ f = fmax Ultra low standby power Automatic power-down when deselected CMOS for optimum speed/power Offered in a 48 Ball BGA Package when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH ), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The addresses must not be toggled once the read is started on the device. Writing to the device is accomplished by taking Chip Enables (CE LOW ) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes Functional Description[1] The CG6257AM is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life(R) (MoBL) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% The device can also be put into standby mode Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array SENSE AMPS I/O0 - I/O7 I/O8 - I/O15 COLUMN DECODER BHE WE OE BLE A11 A12 A13 A14 A15 A16 A17 CE Power- Down Circuit BHE BLE CE Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Weida Semiconductor, Inc. 38-XXXXX Revised August 2003 PRELIMINARY Pin Configuration[2, 3, 4] FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC/ A18 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC/ A20 A B C D E F G H CG6257AM I/O12 GND I/O13 NC/ A19 A8 A14 A12 A9 Note: 2. DNU pins have to be left floating. 3. Ball H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 8M, 16M and a 32M density respectively. 4. NC "no connect" - not connected internally to the die. 38-XXXXX Page - 2 - of 12 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................-65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential................. -0.4V to 4.6V CG6257AM DC Voltage Applied to Outputs in High Z State[5, 6, 7] ........................................-0.4V to 3.3V DC Input Voltage[5, 6, 7].....................................-0.4V to 3.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range[9] Device CG6257AM Range Industrial Ambient Temperature -25C to +85C VCC 2.70V to 3.30V Product Portfolio Power Dissipation Product Min. CG6257AM 2.70 VCC Range (V) Typ.[8] 3.0 Max. 3.30 70 Speed (ns) Typ.[8] 2 Operating ICC(mA) f = 1MHz Max. 4 f = fmax Typ.[8] 13 Max. 17 Standby ISB2(A) Typ.[8] 55 Max. 80 Notes: 5. VIL(MIN) = -0.5V for pulse durations less than 20ns. 6. VIH(Max) = Vcc + 0.5V for pulse durations less than 20ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 9. Vcc must be at minimal operational levels before inputs are turned ON. 38-XXXXX Page - 3 - of 12 PRELIMINARY Electrical Characteristics Over the Operating Range CG6257AM CG6257AM-70 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supplay Voltage Output HIGH Voltage IOH = -1.0 mA Output LOW Voltage IOL = 2.0mA Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current -- CMOS Inputs VCC= 2.7V to 3.3V VCC= 2.7V to 3.3V(F = 0) GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels VCC = 2.70V VCC = 2.70V 0.8*Vcc -0.3 -1 -1 13 2.0 Test Conditions Min. 2.7 2.4 0.4 VCC +0.3V 0.4 +1 +1 17 4 350 Typ.[8] Max. 3.3 Unit V V V V V A A mA mA A ISB1 Vcc = 3.3V CE > VCC-0.2V VIN>VCC-0.2V, VIN<0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.30V Vcc = 3.3V CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V 55 ISB2 Automatic CE Power-Down Current -- CMOS Inputs 80 A Capacitance[10] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance[10] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Note: 10. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board Symbol JA JC BGA 55 16 Unit C/W C/W 38-XXXXX Page - 4 - of 12 PRELIMINARY AC Test Loads and Waveforms VCC OUTPUT R1 VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% CG6257AM 50 pF INCLUDING JIG AND SCOPE Fall Time = 1 V/ns Equivalent o: t THE VENINEQUIVALENT RTH OUTPUT V Unit V Parameters R1 R2 RTH VTH 3.0V VCC 1179 1941 733 1.87 38-XXXXX Page - 5 - of 12 PRELIMINARY Switching Characteristics Over the Operating Range[11] 70 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [13] CG6257AM Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z CE LOW to Low Z CE HIGH to High [12, 14] Min. 70 Max. Unit ns 70 10 70 35 5 25 5 25 70 5 25 0 70 60 60 0 0 45 60 45 0 25 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High Z[12, 14] [12, 14] Z[12, 14] BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[12, 14] BLE / BHE HIGH to HIGH Address Skew Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[12, 14] Low-Z[12, 14] Z[12, 14] Notes: 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section.. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 14. High-Z and Low-Z parameters are characterized and are not 100% tested. . 38-XXXXX Page - 6 - of 12 PRELIMINARY Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tSK CG6257AM tOHA tAA DATA VALID DATA OUT PREVIOUS DATA VALID Read Cycle 2 (OE Controlled) [15, 16] ADDRESS CE tSK tRC tPD tHZCE tACE BHE/BLE tLZBE OE tDBE tHZBE tHZOE HIGH IMPEDANCE ICC ISB DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tPU tLZCE tDOE DATA VALID 50% 50% Note: 15. WE is HIGH for Read Cycle. 16. Addresses should not be toggled after the start of a read cycle 38-XXXXX Page - 7 - of 12 PRELIMINARY Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [13, 14, 17, 18, 19] CG6257AM t WC ADDRESS tSCE CE tSA WE tAW tPWE tHA BHE/BLE tBW OE tSD DATAI/O DON'T CARE tHD VALID DATA tHZOE Write Cycle 2 (CE Controlled) [13, 14, 17, 18, 19] t WC ADDRESS tSCE CE tSA tAW tPWE tHA WE tBW BHE/BLE OE tSD DATAI/O DON'T CARE tHD VALID DATA tHZOE Notes: 17. Data I/O is high impedance if OE = VIH. 18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. 38-XXXXX Page - 8 - of 12 PRELIMINARY Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW) [18, 19] CG6257AM tWC ADDRESS tSCE CE BHE/BLE tBW tAW tHA tSA WE tPWE tSD DATA I/O DON'T CARE tHD tLZWE VALID DATA tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW) [18, 19] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tBW tHA tPWE tSD tHD DATA I/O DON'T CARE VALID DATA 38-XXXXX Page - 9 - of 12 PRELIMINARY Truth Table[20] CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H H L L L L H Inputs/Outputs High Z High Z Data Out (I/O0 - I/O15) Data Out (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data Out (I/O8 - I/O15) High Z High Z High Z Data In (I/O0 - I/O15) Data In (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data In (I/O8 - I/O15) Mode Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write CG6257AM Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Note: 20. H = VIH, L = VIL, X = Don't Care Ordering Information Speed (ns) 70 Ordering Code CG6257AM Package Name BA48K Package Type 48-ball Fine Pitch BGA (6 mm x 8mm x 1.2 mm) Operating Range Industrial 38-XXXXX Page - 10 - of 12 PRELIMINARY Package CG6257AM 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K TOP VIEW BOTTOM VIEW O0.05 M C O0.25 M C A B A1 CORNER 1 2 3 4 5 6 O0.300.05(48X) A1 CORNER 6 5 4 3 2 1 A B D E F G H 0.75 C 8.000.10 8.000.10 5.25 A B C D E 2.625 F G H A B 0.530.05 6.000.10 A 1.875 0.75 3.75 0.25 C 0.210.05 B 0.15 C 0.15(4X) 6.000.10 REFERENCE JEDEC MO-207 SEATING PLANE 0.36 C 1.20 MAX 51-85193-*A MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders 38-XXXXX Page - 11 - of 12 (c) Weida Semiconductor, Inc., 2002. The information contained herein is subject to change without notice. Weida Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Weida Semiconductor product. Nor does it convey or imply any license under patent or other rights. Weida Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Weida Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Weida Semiconductor against all charges. PRELIMINARY Document Title: CG6257AM MoBL3(R) 4Mb (256K x 16) Pseudo Static RAM Document Number: 38-XXXXX REV. ** ECN NO. Issue Date 10/21/03 Orig. of Change MPR Description of Change New Datasheet CG6257AM 38-XXXXX Page - 12 - of 12 |
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